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1 ? file number 4321.4 HI5728 10-bit, 125/60msps , dual high speed cmos d/a converter the HI5728 is a 10-bit, dual 125msps d/a converter which is implemented in an advanced cmos process. it is designed for high speed applications where integration, bandwidth and accuracy are essential. operating from a single +5v or +3v supply, the converter provides 20.48ma of full scale output current and includes an input data register. low glitch energy and excellent frequency domain performance are achieved using a segmented architecture. a 60msps version and an 8-bit (hi5628) version are also available. comparable single dac solutions are the hi5760 (10-bit) and the hi5660 (8-bit). features ? throughput rate . . . . . . . . . . . . . . . . . . . . . . . . 125msps low power . . . . . . . . . . . . . . . 330mw at 5v, 54mw at 3v integral linearity error . . . . . . . . . . . . . . . . . . . . . 1 lsb differential linearity . . . . . . . . . . . . . . . . . . . . . . 0.5 lsb gain matching (typ) . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5% sfdr at 5mhz output . . . . . . . . . . . . . . . . . . . . . . . 68dbc single power supply from +5v to +3v cmos compatible inputs excellent spurious free dynamic range internal voltage reference dual 10-bit d/a converters on a monolithic chip applications wireless local loop direct digital frequency synthesis wireless communications signal reconstruction arbitrary waveform generators test equipment/instrumentation high resolution imaging systems pinout HI5728 (lqfp) top view ordering information part number temp. range ( o c) package pkg. no. max clock speed HI5728in -40 to 85 48 ld lqfp q48.7x7a 125mhz HI5728/6in -40 to 85 48 ld lqfp q48.7x7a 60mhz HI5728eval1 25 evaluation platform 125mhz 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 qd6 qd5 qd4 qd3 qd2 qd1 qd0 (lsb) dv dd dgnd nc av dd agnd id6 id5 id4 id3 id2 sleep dv dd dgnd nc av dd id1 id0 (lsb) id7 id8 id9 (msb) dv dd dgnd qclk dgnd dv dd qd9 (msb) qd8 qd7 iclk agnd icomp1 reflo iouta ioutb agnd agnd qoutb qouta fsadj refio qcomp1 data sheet july 1999 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ? intersil corporation 2000
2 functional block diagram upper voltage reference (lsb) id0 id1 id2 id3 id4 id5 id6 (msb) id9 iclk id7 id8 5-bit decoder refio latch av dd agnd dv dd dgnd latch cascode current source switch matrix bias generation int/ext fsadj reference int/ext select reflo 31 36 36 31 msb segments 5 lsbs + icomp1 sleep iouta ioutb upper (lsb) qd0 qd1 qd2 qd3 qd4 qd5 qd6 qclk qd7 qd8 5-bit decoder latch latch cascode current source switch matrix 31 36 36 31 msb segments 5 lsbs + qcomp1 qouta qoutb HI5728
3 typical applications circuit ioutb iouta 50 ? +5v or +3v supply 0.1 f 50 ? 10 f 50 ? 0.1 f 2k ? ferrite 10 h + bead r set 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 av dd (power plane) id7 id6 id5 id8 id9 (msb) qd9 (msb) id4 id3 id2 id1 id0 (lsb) qd8 qd7 qd6 qd5 qd4 qd3 qd2 qd1 qd0 (lsb) i clk /q clk dv dd 0.1 f dv dd sleep dv dd 0.1 f dv dd dgnd nc (ground) av dd agnd icomp1 0.1 f 0.1 f av dd agnd qouta qoutb 50 ? 50 ? 0.1 f refio qcomp1 0.1 f av dd 0.1 f av dd agnd av dd 0.1 f dv dd dgnd dv dd nc (ground) +5v or +3v supply 0.1 f 10 f ferrite 10 h + bead dv dd (power plane) analog ground plane digital ground plane note: icomp1 and qcomp1 pins (24, 14) must be tied together externally HI5728
4 pin descriptions pin no. pin name pin description 39-30 qd9 (msb) through qd0 (lsb) digital data bit 9, the most significant bit through di gital data bit 0, the least significant bit, of the q channel. 1-6, 48-46 id9 (msb) through id0 (lsb) digital data bit 9, the most significant bit through di gital data bit 0, the least significant bit, of the i channel. 8 sleep control pin for power-down mode. sleep mode is acti ve high; connect to ground for normal mode. sleep pin has internal 20 a active pull-down current. 15 reflo connect to analog ground to enable internal 1.2v reference or connect to av dd to disable. 23 refio reference voltage input if internal reference is disabled and reference voltage output if internal reference is enabled. use 0.1 f cap to ground when internal reference is enabled. 22 fsadj full scale current adjust. use a re sistor to ground to adjust full scale output current. full scale output current per channel = 32 x i fsadj . 14, 24 icomp1, qcomp1 reduces noise. connect each to av dd with 0.1 f capacitor near each pin. the icomp1 and qcomp1 pins must be tied together externally. 13, 18, 19, 25 agnd analog ground connections. 17 ioutb the complimentary current output of the i channel. bits set to all 0s gi ves full scale current. 16 iouta current output of the i channel. bits set to all 1s gives full scale current. 20 qoutb the complimentary current output of the q channel. bits set to all 0s gives full scale current. 21 qouta current output of the q channel. bits set to all 1s gives full scale current. 11, 27 nc no connect. recommended: connect to ground. 12, 26 av dd analog supply (+2.7v to +5.5v). 10, 28, 41, 44 dgnd digital ground. 9, 29, 40, 45 dv dd supply voltage for digital circ uitry (+2.7v to +5.5v). 43 iclk clock input for i channel. positi ve edge of clock latches data. 42 qclk clock input for q channel. positi ve edge of clock latches data. HI5728
5 absolute maximum ratings thermal information digital supply voltage dv dd to dcom . . . . . . . . . . . . . . . . . . +5.5v analog supply voltage av dd to acom . . . . . . . . . . . . . . . . . . +5.5v grounds, acom to dcom . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v digital input voltages (d9-d0, clk, sleep). . . . . . . . . dv dd +0.3v internal reference output current. . . . . . . . . . . . . . . . . . . . . 50 a reference input voltage range . . . . . . . . . . . . . . . . . . av dd +0.3v analog output current (i out ) . . . . . . . . . . . . . . . . . . . . . . . . . 24ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) tqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 maximum power dissipation tqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .930mw maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications av dd = dv dd = + 5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values. data given is per channel except for ?power supply characteristics.? parameter test conditions HI5728in t a = -40 o c to 85 o c units min typ max system performance (per channel) resolution 10 - - bits integral linearity error, inl ?best fit? straight line (note 7) -1 0.5 +1 lsb differential linearity error, dnl (note 7) -0.5 0.25 +0.5 lsb offset error, i os (note 7) -0.025 +0.025 % fsr offset drift coefficient (note 7) - 0.1 - ppm fsr/ o c full scale gain error, fse with external reference (notes 2, 7) -10 2 +10 % fsr with internal reference (notes 2, 7) -10 1 +10 % fsr full scale gain drift with external reference (note 7) - 50 - ppm fsr/ o c with internal reference (note 7) - 100 - ppm fsr/ o c gain matching between channels -0.5 0.1 0.5 db i/q channel isolation f out = 10mhz - 80 - db output voltage compliance range (note 3) -0.3 - 1.25 v full scale output current, i fs 2 - 20 ma dynamic characteristics (per channel) maximum clock rate, f clk (note 3) 125 - - mhz output settling time, (t sett ) 0.1% ( 1 lsb, equivalent to 9 bits) (note 7) - 20 - ns 0.05% ( 1/2 lsb, equivalent to 10 bits) (note 7) - 35 - ns singlet glitch area (peak glitch) r l = 25 ? (note 7) - 35 - pvs output rise time full scale step - 1.5 - ns output fall time full scale step - 1.5 - ns output capacitance - 10 - pf output noise ioutfs = 20ma - 50 - pa/ hz ioutfs = 2ma - 30 - pa/ hz HI5728
6 ac characteristics (per channel) - HI5728in - 125mhz spurious free dynamic range, sfdr within a window f clk = 125msps, f out = 32.9mhz, 10mhz span (notes 4, 7) - 75 - dbc f clk = 100msps, f out = 5.04mhz, 4mhz span (notes 4, 7) - 76 - dbc f clk = 60msps, f out = 10.1mhz, 10mhz span (notes 4, 7) - 75 - dbc f clk = 50msps, f out = 5.02mhz, 2mhz span (notes 4, 7) - 76 - dbc f clk = 50msps, f out = 1.00mhz, 2mhz span (notes 4, 7) - 78 - dbc total harmonic distortion (thd) to nyquist f clk = 100msps, f out = 2.00mhz (notes 4, 7) - 71 - dbc f clk = 50msps, f out = 2.00mhz (notes 4, 7) - 71 - dbc f clk = 50msps, f out = 1.00mhz (notes 4, 7) - 76 - dbc spurious free dynamic range, sfdr to nyquist f clk = 125msps, f out = 32.9mhz, 62.5mhz span (notes 4, 7) - 54 - dbc f clk = 125msps, f out = 10.1mhz, 62.5mhz span (notes 4, 7) - 64 - dbc f clk = 100msps, f out = 40.4mhz, 50mhz span (notes 4, 7) - 52 - dbc f clk = 100msps, f out = 20.2mhz, 50mhz span (notes 4, 7) - 60 - dbc f clk = 100msps, f out = 5.04mhz, 50mhz span (notes 4, 7) - 68 - dbc f clk = 100msps, f out = 2.51mhz, 50mhz span (notes 4, 7) - 74 - dbc f clk = 60msps, f out = 10.1mhz, 30mhz span (notes 4, 7) - 63 - dbc f clk = 50msps, f out = 20.2mhz, 25mhz span (notes 4, 7) - 55 - dbc f clk = 50msps, f out = 5.02mhz, 25mhz span (notes 4, 7) - 68 - dbc f clk = 50msps, f out = 2.51mhz, 25mhz span (notes 4, 7) - 73 - dbc f clk = 50msps, f out = 1.00mhz, 25mhz span (notes 4, 7) - 73 - dbc ac characteristics (per channel) - HI5728/6in - 60mhz spurious free dynamic range, sfdr within a window f clk = 60msps, f out = 10.1mhz, 10mhz span (notes 4, 7) - 75 - dbc f clk = 50msps, f out = 5.02mhz, 2mhz span (notes 4, 7) - 76 - dbc f clk = 50msps, f out = 1.00mhz, 2mhz span (notes 4, 7) - 78 - dbc total harmonic distortion (thd) to nyquist f clk = 50msps, f out = 2.00mhz (notes 4, 7) - 71 - dbc f clk = 50msps, f out = 1.00mhz (notes 4, 7) - 76 - dbc spurious free dynamic range, sfdr to nyquist f clk = 60msps, f out = 20.2mhz, 30mhz span (notes 4, 7) - 56 - dbc f clk = 60msps, f out = 10.1mhz, 30mhz span (notes 4, 7) - 63 - dbc f clk = 50msps, f out = 20.2mhz, 25mhz span (notes 4, 7) - 55 - dbc f clk = 50msps, f out = 5.02mhz, 25mhz span (notes 4, 7) - 68 - dbc f clk = 50msps, f out = 2.51mhz, 25mhz span (notes 4, 7) - 73 - dbc f clk = 50msps, f out = 1.00mhz, 25mhz span (notes 4, 7) - 73 - dbc f clk = 25msps, f out = 5.02mhz, 25mhz span (notes 4, 7) - 71 - dbc voltage reference internal reference voltage, v fsadj voltage at pin 22 with internal reference 1.04 1.16 1.28 v internal reference voltage drift - 60 - ppm / o c internal reference output current sink/source capability - 0.1 - a reference input impedance - 1 - m ? reference input multiplying bandwidth (note 7) - 1.4 - mhz digital inputs d9-d0, clk (per channel) input logic high voltage with 5v supply, v ih (note 3) 3.5 5 - v electrical specifications av dd = dv dd = + 5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values. data given is per channel except for ?power supply characteristics.? (continued) parameter test conditions HI5728in t a = -40 o c to 85 o c units min typ max HI5728
7 input logic high voltage with 3v supply, v ih (note 3)s 2.1 3 - v input logic low voltage with 5v supply, v il (note 3) - 0 1.3 v input logic low voltage with 3v supply, v il (note 3) - 0 0.9 v input logic current, i ih -10 - +10 a input logic current, i il -10 - +10 a digital input capacitance, c in - 5 - pf timing characteristics (per channel) data setup time, t su see figure 41 (note 3) 3 - - ns data hold time, t hld see figure 41 (note 3) 3 - - ns propagation delay time, t pd see figure 41 - 1 - ns clk pulse width, t pw1 , t pw2 see figure 41 (note 3) 4 - - ns power supply characteristics avdd power supply (notes 8, 9) 2.7 5.0 5.5 v dvdd power supply (notes 8, 9) 2.7 5.0 5.5 v analog supply current (i avdd ) (5v or 3v, ioutfs = 20ma) - 46 60 ma (5v or 3v, ioutfs = 2ma) - 8 - ma digital supply current (i dvdd ) (5v, ioutfs = don?t care) (note 5) - 6 10 ma (3v, ioutfs = don?t care) (note 5) - 3 - ma supply current (i avdd ) sleep mode (5v or 3v, ioutfs = don?t care) - 3.2 6 ma power dissipation (5v, ioutfs = 20ma) (note 6) - 330 - mw (5v, ioutfs = 2ma) (note 6) - 140 - mw (3v, ioutfs = 20ma) (note 6) - 170 - mw (3v, ioutfs = 2ma) (note 6) - 54 - mw (5v, ioutfs = 20ma) (note 10) - 300 - mw (3.3v, ioutfs = 20ma) (note 10) - 150 - mw (3v, ioutfs = 20ma) (note 10) - 135 - mw power supply rejection single supply (note 7) -0.2 - +0.2 % fsr/v notes: 2. gain error measured as the error in the ratio between the full scale output current and the current through r set (typically 625 a). ideally the ratio should be 32. 3. parameter guaranteed by design or c haracterization and not production tested. 4. spectral measurements made with diffe rential coupled transformer and 100% amplitude. 5. measured with the clock at 50msps and the output frequency at 1mhz, both channels. 6. measured with the clock at 100msps and the output frequency at 40mhz, both channels. 7. see ?definition of specifications?. 8. for operation below 3v, it is recommended that the output current be reduced to 12ma or less to maintain optimum performance. d v dd and av dd do not have to be equal. 9. for operation above 125mhz, it is recommended that the power suppl y be 3.3v or greater. the part is functional with the clock a bove 125msps and the power supply below 3. 3v, but performance is degraded. 10. measured with the clock at 60msps and the output frequency at 10mhz, both channels. electrical specifications av dd = dv dd = + 5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values. data given is per channel except for ?power supply characteristics.? (continued) parameter test conditions HI5728in t a = -40 o c to 85 o c units min typ max HI5728
8 typical performance curves, 5v power supply figure 1. sfdr vs f out , clock = 5msps figure 2. sfdr vs f out , clock = 25msps figure 3. sfdr vs f out , clock = 50msps figure 4. sfdr vs f out , clock =100msps figure 5. sfdr vs f out , clock = 125msps figure 6. sfdr vs amplitude, f clk / f out = 10 80 75 70 65 60 55 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 output frequency (mhz) -12dbfs 0dbfs -6dbfs sfdr (dbc) 76 74 72 70 sfdr (dbc) 68 66 64 60 12345678910 output frequency (mhz) 62 -12dbfs -6dbfs 0dbfs 80 75 70 65 60 55 0 2 4 6 8 10 1214161820 output frequency (mhz) sfdr (dbc) -12dbfs 0dbfs -6dbfs 75 70 65 60 55 50 45 0 5 10 15 20 25 30 35 40 45 output frequency (mhz) sfdr (dbc) -12dbfs -6dbfs 0dbfs 75 70 65 60 55 50 45 0 5 10 15 20 25 30 35 40 45 50 output frequency (mhz) sfdr (dbc) -12dbfs 6dbfs 0dbfs 80 75 70 65 60 55 50 45 sfdr (dbc) -25 -20 -15 -10 -5 0 amplitude (dbfs) 125msps 100msps 50msps 25msps HI5728
9 figure 7. sfdr vs amplitude, f clk / f out = 5 figure 8. sfdr vs amplitude of two tones, f clk / f out = 7 figure 9. sfdr vs i out , clock = 100msps figure 10. differential vs single-ended, clock = 100msps figure 11. sfdr vs temperature, clock = 100msps figure 12. single tone sfdr typical performance curves, 5v power supply (continued) 80 75 70 65 sfdr (dbc) 60 55 50 45 40 -25 -20 -15 -10 -5 0 amplitude (dbfs) 125msps 100msps 50msps 25msps 75 70 65 60 55 50 45 40 sfdr (dbc) -25 -20 -15 -10 -5 0 amplitude (total peak power of combined tones) (dbfs) 125msps (16.9/18.1mhz) 100msps (13.5/14.5mhz) 50msps (6.75/7.25mhz) 25msps (3.38/3.63mhz) 75 70 65 60 55 50 45 40 sfdr (dbc) 2 4 6 8 10 12 14 16 18 20 i out (ma) 2.5mhz 10mhz 20mhz 40mhz 75 70 65 60 55 50 45 0 5 10 15 20 25 30 35 40 output frequency (mhz) sfdr (dbc) -6dbfs diff 0dbfs diff -6dbfs single 0dbfs single 80 75 70 65 60 55 50 45 40 -40-200 20406080 temperature ( o c) sfdr (dbc) 40.4mhz 10.1mhz 2.5mhz -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 5mhz/div. 50 amp (db) frequency (mhz) sfdr = 64dbc = 100msps fout = 9.95mhz amplitude = 0dbfs 14db external analyzer attenuation f clk = 100msps f out =9.95mhz amplitude = 0dbfs sfdr = 64dbc 14db external analyzer attenuation 5mhz/div. frequency (mhz) amp (db) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 50 HI5728
10 figure 13. two tone, clock = 100msps figure 14. four-tone, clock = 100msps figure 15. eight-tone, clock = 100msps figure 16. four-tone, clock = 50msps figure 17. differential nonlinearity figure 18. integral nonlinearity typical performance curves, 5v power supply (continued) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 0 5mhz / div. 50 amp (db) frequency (mhz) mtpr = 62.9dbc fclk = 100msps fout = 13.5/14.5mhz combined peak amplitude = 0dbfs 14db external anal yzer attenuation amp (db) 0 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 50 f clk = 100msps f out = 13.5/14.5mhz combined peak sfdr = 62.9dbc 14db external amplitude = 0dbfs analyzer attenuation 5mhz/div. frequency (mhz) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0.5 1.45mhz / div. 15 amp (db) sfdr = 71.4dbc f clk = 100msps f out = 3.8,4.4,5.6,6.2mhz combined peak amplitude = 0dbfs (in a window) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 0.5 1.95mhz/div. 20 amp (db) frequency (mhz) sfdr = 67dbc (in a window) f clk = 100msps f out = 2.6,3.2,3.8,4.4,5.6,6.2,6.8mhz combined peak amplitude = 0dbfs -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0.5 950khz/div. 10 amp (db) frequency (mhz) sfdr = 73.6dbc f clk = 50msps f out = 1.9,2.2,2.8,3.1mhz combined peak amplitude = 0dbfs (in a window) -0.4 -0.2 0 0.2 0.4 0 200 400 600 800 1000 lsb code -0.4 -0.2 0 0.2 0.4 0 200 400 600 800 1000 lsb code HI5728
11 figure 19. power vs clock rate, f clk / f out = 10, i out = 20ma typical performance curves, 5v power supply (continued) 210 220 230 240 250 260 270 280 290 300 310 320 0 20 40 60 80 100 120 power (mw) clock rate (msps) typical performance curves, 3v power supply figure 20. sfdr vs f out , clock = 5msps figure 21. sfdr vs f out , clock = 25msps figure 22. sfdr vs f out , clock = 50msps figure 23. sfdr vs f out , clock = 100msps 50 55 60 65 70 75 80 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 output frequency (mhz) -6dbfs 0dbfs -12dbfs sfdr (dbc) 60 65 70 75 80 1 2 3 4 5 6 7 8 9 10 sfdr (dbc) output frequency (mhz) 0dbfs -6dbfs -12dbfs 50 55 60 65 70 75 80 0 2 4 6 8 10 12 14 16 18 20 sfdr (dbc) output frequency (mhz) -12dbfs 0dbfs -6dbfs 45 50 55 60 65 70 75 80 0 5 10 15 20 25 30 35 40 45 sfdr (dbc) output frequency (mhz) 0dbfs -6dbfs -12dbfs HI5728
12 figure 24. sfdr vs f out , clock = 125msps figure 25. sfdr vs amplitude, f clk / f out = 10 figure 26. sfdr vs amplitude, f clk / f out = 5 figure 27. sfdr vs amplitude of two tones, f clk /f out = 7 figure 28. sfdr vs i out , clock = 100msps figure 29. differential vs single-ended, clock = 100msps typical performance curves, 3v power supply (continued) 45 50 55 60 65 70 75 80 0 5 10 15 20 25 30 35 40 45 50 sfdr (dbc) output frequency (mhz) 0dbfs -6dbfs -12dbfs 45 50 55 60 65 70 75 80 -25 -20 -15 -10 -5 0 sfdr (dbc) amplitude (dbfs) 125msps 100msps 50msps 25msps 40 45 50 55 60 65 70 75 80 -25 -20 -15 -10 -5 0 sfdr (dbc) amplitude (dbfs) 25msps 50msps 100msps 125msps 5msps 2 5 a n d 5 0 m s p s 40 45 50 55 60 65 70 75 -25 -20 -15 -10 -5 0 sfdr (dbc) amplitude (dbfs) 25msps (3.38/3.63mhz) 100msps (13.5/14.5mhz) 50msps (6.75/7.25mhz) 125msps (16.9/18.1mhz) 45 50 55 60 65 70 75 80 2 4 6 8 10 12 14 16 18 20 sfdr (dbc) i out (ma) 40mhz 20mhz 10mhz 2.5mhz 45 50 55 60 65 70 75 80 0 5 10 15 20 25 30 35 40 sfdr (dbc) output frequency (mhz) -6dbfs single 0dbfs single -6dbfs diff 0dbfs diff HI5728
13 figure 30. sfdr vs temperature, clock = 100msps figure 31. single tone sfdr figure 32. two-tone, clock = 100msps figure 33. four-tone, clock = 100msps figure 34. eight-tone, clock = 100msps figure 35. four-tone, clock = 50msps typical performance curves, 3v power supply (continued) 40 45 50 55 60 65 70 75 80 -40 -20 0 20 40 60 80 sfdr (dbc) temperature ( o c) 10.1mhz 40.4mhz 2.5mhz -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 5mhz/div. 50 amp (db) frequency (mhz) sfdr = 63dbc f clk = 100msps f out = 9.95mhz amplitude = 0dbfs 14db external analyzer attenuation -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 0 5mhz/div. 50 amp (db) frequency (mhz) sfdr = 61.5dbc f clk = 100msps f out = 13.5/14.5mhz combined peak 14db external analyzer attenuation amplitude = 0dbfs -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0.5 1.45mhz/div. 15 amp (db) frequency (mhz) sfdr = 70.6dbc f clk = 100msps f out = 3.8,4.4,5.6,6.2mhz combined peak amplitude = 0dbfs (in a window) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 0.5 1.95mhz/div. 20 amp (db) frequency (mhz) sfdr = 67.4dbc f clk = 100msps f out = 2.6, 3.2, 3.8, 4.4, combined peak amplitude = 0dbfs (in a window) 5.6, 6.2, 6.8mhz -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 950khz/div. 10 amp (db) frequency (mhz) sfdr = 74.2dbc f clk = 50msps f out = 1.9, 2.2, 2.8, 3.1mhz combined peak amplitude = 0dbfs (in a window) HI5728
14 figure 36. differential nonlinearity figure 37. integral nonlinearity figure 38. power vs clock rate, f clk / f out = 10, i out = 20ma typical performance curves, 3v power supply (continued) -0.4 -0.2 0 0.2 0.4 0 200 400 600 800 1000 lsb code -0.4 -0.2 0 0.2 0.4 0 200 400 600 800 1000 lsb code 120 124 128 132 136 140 144 148 152 0 20 40 60 80 100 120 power (mw) clock rate (msps) HI5728
15 definition of specifications integral linearity error, inl , is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. differential linearity error, dnl, is the measure of the step size output deviation from code to code. ideally the step size should be 1 lsb. a dnl specification of 1 lsb or less guarantees monotonicity. output settling time, is the time required for the output voltage to settle to within a specified error band measured from the beginning of th e output trans ition. the measurement was done by switching from code 0 to 256, or quarter scale. termination impedance was 25 ? due to the parallel resistance of the output 50 ? and the oscilloscope?s 50 ? input. this also aids the ability to resolve the specified error band without overdriving the oscilloscope. singlet glitch area, is the switching transient appearing on the output during a code transition. it is measured as the area under the overshoot portion of the curve and is expressed as a volt-time specif ication. this is tested under the same conditions as ?output settling time.? timing diagrams figure 39. output settling time diagram figure 40. peak glitch area (singlet) measurement method figure 41. propagation delay, setup time, hold time and minimum pulse width diagram clk d9-d0 i out 50% t sett 1 lsb error band t pd v t(ps) height (h) width (w) glitch area = 1 / 2 (h x w) clk d9-d0 i out 50% t pw1 t pw2 t su t hld t su t su t pd t pd t pd t hld t hld t sett t sett t sett HI5728
16 full scale gain error , is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through r set ). full scale gain drift, is measured by setting the data inputs to all ones and measuring the output voltage through a known resistance as the temperature is varied from t min to t max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (full scale range) per o c. total harmonic distortion, thd , is the ratio of the dac output fundamental to the rms sum of the first five harmonics. spurious free dynamic range, sfdr , is the amplitude difference from the fundamental to the largest harmonically or non-harmonically related spur within the specified window. output voltage compliance range, is the voltage limit imposed on the output. the output impedance load should be chosen such that the voltage developed does not violate the compliance range. offset error, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance. offset error is defined as the maximum deviation of the output current from a value of 0ma. offset drift, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance as the temperature is varied from t min to t max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (full scale range) per o c. power supply rejection, is measured using a single power supply. its nominal +5v is varied 10% and the change in the dac full scale output is noted. reference input multiplying bandwidth, is defined as the 3db bandwidth of the voltage reference input. it is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. the frequency is increased until the amplitude of the output waveform is 0.707 of its original value. internal reference voltage drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm per o c. detailed description the HI5728 is a dual, 10-bit, current out, cmos, digital to analog converter. its maximu m update rate is 125msps and can be powered by either single or dual power supplies in the recommended range of +3v to +5v. it consumes less than 330mw of power when using a +5v supply with the data switching at 100msps. the architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. the five msbs are represented by 31 major current sources of equivalent current. the five lsbs are comprised of binary weighted current sources. consider an input waveform to the converter which is ramped through all the codes from 0 to 1023. the five lsb current sources would begin to count up. when they reached the all high state (decimal value of 31) and needed to count to the next code, they would all turn off and the first major current source would turn on. to continue counting upward, the 5 lsbs would count up another 31 codes, and then the next major current source would turn on and the five lsbs would all turn off. the process of the single, equivalent, major current source turning on and the five lsbs turning off each time the converter reaches another 31 codes greatly reduces the glitch at any one switching point. in previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst- case transition points such as mid-scale and quarter scale transitions. by greatly reducing the amount of current switching at certain ?major? transitions, the overall glitch of the converter is dramatically reduced, improving settling times and transient problems. digital inputs and termination the HI5728 digital inputs are guaranteed to cmos levels. however, ttl compatibility can be achieved by lowering the supply voltage to 3v due to the digital threshold of the input buffer being approximately half of the supply voltage. the internal register is updated on th e rising edge of the clock. to minimize reflections, proper termination should be implemented. if the lines driv ing the clock(s) and digital inputs are 50 ? lines, then 50 ? termination resistors should be placed as close to the converter inputs as possible. ground plane(s) if separate digital and analog ground planes are used, then all of the digital functions of the device and their corresponding components should be over the digital ground plane and terminated to the digital ground plane. the same is true for the analog components and the analog ground plane. refer to the application note on the HI5728 evaluation board for further discussion of the ground plane(s) upon availability. noise reduction to minimize power supply noise, 0.1 f capacitors should be placed as close as possible to the converter?s power supply pins, av dd and dv dd . also, should the layout be designed using separate digital and analog ground planes, these capacitors should be terminated to the digital ground for dv dd and to the analog ground for av dd . additional filtering of the power supplies on the board is recommended. see the application note on the HI5728 evaluation board for more information upon availability. HI5728
17 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com voltag e reference the internal voltage reference of the device has a nominal value of +1.2v with a 60 ppm / o c drift coefficient over the full temperature range of the converter. it is recommended that a 0.1 f capacitor be placed as close as possible to the refio pin, connected to the analog ground. the reflo pin (15) selects the reference. the internal reference can be selected if pin 15 is tied low (ground). if an external reference is desired, then pin 15 should be tied high (to the analog supply voltage) and the external reference driven into refio, pin 23. the full scale output current of the conver ter is a function of the voltage reference used and the value of r set . i out should be within the 2ma to 20ma range, through operation below 2ma is possible, with performance degradation. if the internal reference is used, v fsadj will equal approximately 1.16v (pin 22). if an external reference is used, v fsadj will equal the external reference. the calculation for i out (full scale) is: i out (full scale) = (v fsadj /r set ) x 32. if the full scale output current is set to 20ma by using the internal voltage reference (1.16v) and a 1.86k ? r set resistor, then the input coding to output current will resemble the following: outputs iouta and ioutb (or qouta and qoutb) are complementary current outputs. the sum of the two currents is always equal to the full scale output current minus one lsb. if single ended use is desired, a load resistor can be used to convert the output current to a voltage. it is recommended that the unused output be either grounded or equally terminated. the voltage developed at the output must not violate the output voltage compliance range of -0.3v to 1.25v. r load should be chosen so that the desired output voltage is produced in conjunction with the output full scale current, which is described above in the ?reference? section. if a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. the output voltage equation is: v out = i out x r load . these outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. the sfdr measurements in this data sheet were performed with a 1:1 transformer on the output of the dac (see figure 1). with the center tap grounded, th e output swing of pins 16 and 17 will be biased at zero volts. it is important to note here that the negative voltage output compliance range limit is -300mv, imposing a maximum of 600mv p-p amplitude with this configuration. the load ing as shown in figure 1 will result in a 500mv signal at th e output of the transformer if the full scale output current of the dac is set to 20ma. v out = 2 x i out x r eq , where r eq is ~12.5 ? . allowing the center tap to float will result in identical transformer output, however the output pins of the dac will have positive dc offset. the 50 ? load on the output of the transformer represents the spectrum analyzer?s input impedance. table 1. input coding vs output current (per dac) input code (d9-d0) iouta (ma) ioutb (ma) 11111 11111 20 0 10000 00000 10 10 00000 00000 0 20 pin 17 (20) pin 16 (21) v out = (2 x i out x r eq )v 100 ? 50 ? 50 ? 50 ? ioutb (qoutb) iouta (qouta) figure 42. HI5728

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